Interrupts and Exceptions: Types of interrupts. Interrupt handling, interrupt vectors, software interrupts, IRQ Interrupt vector

Signs of pregnancy after embryo implantation

The operating system is largely controlled by the interrupt system. In real mode, there are 2 types of interrupts: hardware and software. Software interrupts are initialized with the int instruction. Hardware - external events asynchronous with respect to the program being executed. Typically, hardware interrupts are initiated by the I/O hardware after the current operation has finished executing.

To process interrupts in real mode, the processor uses an interrupt vector table. The segment addresses used to locate interrupt handlers are called interrupt vectors.

The interrupt vector table is located at the very beginning of the OP, i.e. its physical address = 0. The interrupt vector table consists of 256 elements of 4 bytes. Vectors consist of a 16-bit segment address and a 16-bit offset (first comes the offset and then the segment). Each interrupt vector has a number, called the interrupt number, which indicates its place in the table. This number multiplied by 4 gives the absolute address of the memory vector.

Interrupt vectors get their values ​​at system startup. First, the BIOS, performing initialization procedures, sets the values ​​of certain interrupt vectors. When DOS boots, DOS interrupt vectors are set.

DOS can remap some of the BIOS vectors to its routines. The user can also change the values ​​of the interrupt vectors. When a software or hardware interrupt occurs, the current state of the CS:IP registers, as well as the values ​​of the flag register, are written to the program stack. Next, new CS:IP values ​​are selected from the interrupt vector table. In this case, control is transferred to the interrupt handling procedure.

Before entering the interrupt routine, the trace flag TF and the interrupt enable flag IF are forced to clear. After completing the interrupt processing, the procedure should issue an IRET instruction, which will pop the values ​​of the CS:IP registers and the flags register from the stack. Then the execution of the interrupted program continues.

The interrupt handling procedure must necessarily end with the IRET procedure, after which the flags, CS, IP values ​​are read.

Interrupt (interrupt) - an event that requires an immediate response from the processor. The reaction is that the processor interrupts the processing of the current program ( program to be interrupted) and proceeds to execute some other program ( interrupt program) specially designed for this event. Upon completion of this program, the processor returns to the execution of the interrupted program.

Each event requiring interruption is followed by interrupt signal, notifying the computer about this, and called interrupt request.

Program status represents a set of states of all memory elements at the corresponding time (for example, after the execution of the last command). When an interrupt occurs, the microcontroller stores the contents of the program counter on the stack and loads the address of the corresponding interrupt vector into it. The last instruction of the interrupt service routine must be an instruction that returns to the main program and restores the previously saved program counter. During the execution of the interrupt handler, some information may be changed. Therefore, when passing to the interrupt handler, it is necessary to save the elements that are being changed. The set of such elements is program state vector. In this case, other information about the state of the memory cells is not significant or can be restored by software.

Initial state vector contains all the necessary information for the initial launch of the program. In many cases, the initial state vector contains only one element - the starting address of the program being run.

Interrupt vector is the initial state vector of the interrupting program (handler) and contains all the necessary information to jump to the handler, including its starting address. Each type of interrupt has its own interrupt vector, which initializes the execution of the corresponding handler. Usually, interrupt vectors are stored in specially allocated fixed memory cells with short addresses, which are interrupt vector table. To jump to the corresponding interrupt program, the processor must have an interrupt vector and the address of this vector. At this address, as a rule, there is an unconditional jump command to the interrupt service routine.

As a rule, storage and return control is assigned to the interrupt handler. In this case, the handler consists of three parts - preparatory ( prologue ) and final ( epilogue ), providing switching programs, and the actual interrupting program that performs the operations requested by the request. Response time is defined as the time interval from the moment an interrupt request is received to the start of execution of the interrupting program.


tp is the response time of the system to an interrupt;
t– time of storing the state of the interrupted program;
t ppr is the time of the actual interrupting program;
t in– recovery time of the interrupted program state

If there are several sources of requests, a certain order of servicing incoming requests must be established, called priority ratios or service discipline. The set of all possible types of processor interrupt is interrupt system microcontroller. The service discipline determines which of several requests that arrive at the same time is to be processed first, and whether this request has the right to interrupt one or another interrupt handler.
If an interrupt request with a higher priority level is received during interrupt processing, control is transferred to the higher priority interrupt handler, while the work of the interrupt handler with a lower priority level is suspended. Arises interrupt nesting. The maximum number of programs that can suspend each other is called interruption depth.

If the interrupt request is not serviced by the time a new request arrives from the same source (same priority), then interrupt system saturation. In this case, part of the interrupt requests will be lost, which is unacceptable for the normal operation of the microcontroller.

Interrupt system characteristics are:

  • total number of interrupt requests – number of interrupt request sources;
  • type of interrupt representation - as a rule, an interrupt request is represented by a logical signal level;
  • interrupt priority - determines the order in which each interrupt request is processed, the higher the priority, the lower the delay in the execution of the interrupt program for it;
  • reaction time - the time interval between the appearance of an interrupt request and the start of the interrupt program execution;
  • interrupt delay - determined by the total time for storing and restoring the program;
  • depth, usually the same as the number of priority levels in the interrupt system;
  • saturation of the interrupt system;
  • allowable interruption times for programs (usually the end of the execution of the next instruction).

Interrupt masking is used to tell the microcontroller to react to each type of interrupt or ignore it. The interrupt mask represents a binary code whose bits are mapped to interrupt request sources. A single bit in binary code tells the microcontroller to handle this type of interrupt. The zero bit, on the contrary, does not allow the microcontroller to proceed to the processing of interrupts of the specified type.
As a rule, in addition to masking interrupts, there is also a global interrupt enable bit, the zero value of which disables all interrupt handlers (except for hardware reset and jump to the beginning of the executable program).
In addition to the interrupt mask binary, there is also a binary code interrupt flags, which allows the interrupt handler to set the source of the interrupt if there are several sources with the specified request in the microcontroller.

Interrupts are best suited for handling events that occur asynchronously with respect to program execution. An interrupt can be viewed as some special event in the system that requires an immediate response.

Almost all I/O systems in a computer operate using interrupts. In particular, when you press keys or click the mouse, the hardware generates interrupts. In response to them, the system, respectively, reads the code of the pressed key or remembers the coordinates of the mouse cursor. Interrupts are generated by the disk controller, LAN adapter, serial ports, audio adapter, and other devices.

It seems obvious that a wide variety of interruptions are possible for a wide variety of reasons. Therefore, a number is associated with an interrupt - the so-called interrupt number.

This number uniquely corresponds to a particular event. The system is able to recognize interrupts and, when they occur, starts the procedure corresponding to the interrupt number.

Some interrupts (the first five in numerical order) are reserved for use by the CPU in case of any special events such as an attempt to divide by zero, overflow, etc.

Programs can themselves call interrupts with a given number. To do this, they use the INT command. These are the so-called software interrupts. Software interrupts are not asynchronous, as they are called from the program.

It is convenient to use software interrupts to organize access to individual functions common to all programs. For example, operating system functions are available to application programs through interrupts. When calling these modules, it is not necessary to know their current address in memory.

Application programs and drivers can install their own interrupt handlers for later use by other programs. To do this, embedded interrupt handlers must be resident in memory.

Hardware interrupts are caused by physical devices and therefore come asynchronously with respect to the execution of any programs. These interrupts inform the system about device related events. For example, that the printing of a character on the printer has finally completed and it would be nice to issue the next character, or that the disk sector has already been read and its contents are available to the program.

The use of interrupts when working with slow external devices allows you to combine input / output with data processing in the central processor. As a result, the overall performance of the system is improved.

Sometimes it is desirable to make the system insensitive to all or some hardware interrupts. To do this, use the so-called interrupt masking, which we will talk about later. But there is also a non-maskable interrupt (which, by the way, can still be masked, or, more precisely, blocked).

Note that interrupt handlers can themselves trigger software interrupts, for example, to access a BIOS or MS-DOS service.

Writing your own interrupt handlers and replacing the standard MS-DOS and BIOS handlers is quite a challenge. It is necessary to take into account all the subtleties of the operation of the equipment, as well as the interaction of software and hardware. Debugging can destroy the operating system with unpredictable consequences, so you need to be very careful about what your program does.

4.1. Interrupt vector table

In order to associate the address of the interrupt handler with the interrupt number, the interrupt vector table is used, which occupies the first kilobyte of RAM. This table is in the address range from 0000:0000 to 0000:03FFh and consists of 256 entries - far addresses of interrupt handlers.

The entries in the interrupt vector table are called interrupt vectors. The first word of the table entry contains the offset component, and the second word contains the segment component of the interrupt handler address.

Interrupt vector 0 is at 0000:0000, interrupt vector 1 is at 0000:0004, and so on.

For a C programmer, the interrupt vector table can be described as follows:

void (far* interrupt_table)();

Table initialization is performed partly by the BIOS basic input/output system after testing the hardware and before the operating system starts booting, partly when MS-DOS boots. The MS-DOS operating system can change some of the interrupt vectors set by the BIOS.

Let's talk about the assignment of the most important interrupt vectors.

Number Description
0 Division Error. Called automatically after the execution of the DIV or IDIV commands, if the division results in an overflow (for example, when dividing by 0). Typically, when this interrupt is handled, MS-DOS displays an error message and stops the program from running. In this case, for the i8086 processor, the return address points to the instruction following the division instruction, and for the i80286 processor and older models, to the first byte of the instruction that caused the interrupt
1 Stepping interrupt. Generated after each machine instruction is executed if the step trace bit TF is set in the flags word. Used for debugging programs. This interrupt is not generated after transferring data to segment registers with MOV and POP instructions.
2 Hardware NMI. This interrupt can be used differently in different machines. It is usually generated when a parity error occurs in RAM and when an interrupt is requested from the coprocessor.
3 Trace interrupt. Thrown when executing a single-byte machine instruction with code CCh and is commonly used by debuggers to set a breakpoint
4 Overflow. Generated by the INTO machine instruction if the OF overflow flag is set. If the flag is not set, the INTO command is executed as NOP. This interrupt is used to handle errors when performing arithmetic operations.
5 Print a copy of the screen. Fired when the user has pressed a key In MS-DOS programs, it is commonly used to print a screen image. For the i80286 processor and above, it is generated when the BOUND machine instruction is executed if the value being checked is outside the specified range
6 Undefined opcode or instruction length greater than 10 bytes
7 Special case of no arithmetic coprocessor
8
9 IRQ1 - keyboard interrupt. Emitted when the user presses and releases keys. Used to read data from the keyboard
A
B
C
D IRQ5 - hard disk controller interrupt (IBM PC/XT computers only)
E IRQ6 - an interrupt is generated by the floppy disk controller after the completion of the I / O operation
F IRQ7 - interrupt from parallel adapter. Generated when the printer connected to the adapter is ready to perform the next operation. Usually not used
10 Video adapter maintenance
11 Determining the configuration of devices in the system
12 Determining the size of RAM
13 Disk system maintenance
14 Working with an asynchronous serial adapter
15 Advanced Service
16 Keyboard Maintenance
17 Printer Maintenance
18 Run BASIC in ROM if available
1A Watch service
1B Interrupt handler that occurs when the user presses a key combination
1C Software interrupt, called 18.2 times per second by the timer hardware interrupt handler
1D Video table address for 6845 video adapter controller
1E Pointer to floppy parameter table
1F Pointer to graphics table for ASCII characters 128-255
20-5F Used by MS-DOS or reserved for MS-DOS
60-67 Interrupts reserved for user programs
68-6F Not used
70
71
72 IRQ10 - reserved
73 IRQ11 - reserved
74 IRQ12 - reserved
75
76
77 IRQ15 - reserved
78-7F Not used
80-85 Reserved for BASIC
86-F0 Used by the BASIC interpreter
F1-FF Not used

Interrupts labeled IRQ0 - IRQ15 are hardware interrupts.

4.2. Interrupt masking

Often, when executing critical sections of programs, it is necessary to disable interrupts in order to guarantee the uninterrupted execution of a certain sequence of instructions. This can be done with the CLI command. It must be placed at the beginning of the critical instruction sequence, and at the end, place the STI instruction, which allows the processor to accept interrupts. The CLI command disables only maskable interrupts; this command does not affect the processing of a non-maskable interrupt.

If you are using the CLI command to disable interrupts, be careful not to disable interrupts for an extended period of time, as this can lead to undesirable consequences. For example, to the lag of the system clock or the malfunctioning of computer peripherals.

If you need to disable not all interrupts, but only some, for example, from the keyboard, then for this you need to use the services of an interrupt controller. By writing certain control information to this controller, interrupts from individual devices can be masked.

4.3. Changing the Interrupt Vector Table

Your program may need to handle some interrupts. To do this, the program must install the vectors of the necessary interrupts on its handler. This can be done by changing the contents of the corresponding entry in the interrupt vector table.

It is very important not to forget to restore the contents of the modified vectors in the interrupt table before shutting down.

The fact is that the memory that was allocated to the program is freed after the program ends. It can be used, for example, to download another program. If you forget to restore the vector and an interrupt occurs, then the system may crash - the vector now points to an area that can contain anything.

Therefore, the sequence of actions for non-resident programs that want to handle interrupts should be as follows:

  • read the contents of the interrupt vector table element for the vector with the number you need;
  • store this content (the address of the old interrupt handler) in the program data area;
  • set the new address in the interrupt vector table to point to the start of your interrupt handler;
  • before terminating the program, read the address of the old interrupt handler from the data area and write it to the interrupt vector table.

In addition, the operation of changing the interrupt vector must be continuous in the sense that no interrupt must occur during the change. If, for example, you write a new offset value, but you do not have time to update the segment address, then to which address will control be transferred in the event of an interrupt, and what will happen? This can only be guessed at.

MS-DOS Interrupt Table Functions

To facilitate the job of swapping interrupt vectors, MS-DOS provides you with special functions to read an entry in the interrupt vector table and write a new address to it. If you use these functions, MS-DOS guarantees that the vector replacement operation will be performed correctly. You don't have to worry about the continuity of the interrupt vector replacement process.

To read the vector, use the INT 21h interrupt function 35h. Before calling it, the AL register must contain the vector number in the table. After the function is executed, the ES:BX registers will contain the desired address of the interrupt handler.

For the vector number in the AL register, the INT 21h interrupt function 25h sets a new interrupt handler. The interrupt handler address must be passed through the DS:DX registers.

Of course, you can also access the interrupt vector table directly, but then when writing, you must mask the interrupts with the CLI command, remembering to enable them after writing with the STI command.

For C users, the _dos_getvect and _dos_setvect functions are available. The first function gets the address from the interrupt vector table, the second sets the new address. Both of these functions access the INT 21h interrupt functions 35h and 25h described above.

What are the requirements for an interrupt handler?

If interrupts occur frequently, their handling can greatly slow down the application program. Therefore, an interrupt handler should be a short, fast-running program that does only the most necessary things. For example, reading the next character from the printer port and writing it to the buffer, increasing the value of some global interrupt counter, etc.

Interrupt handler chains

If you need to add some custom actions to those performed by the standard interrupt handler, then you can organize a chain of interrupts.

To organize an interrupt chain, you need to write the address of your handler to the vector table, remembering to save the previous contents of the table. Your handler receives interrupt control, performs some action, then passes control to the old handler.

Another way to do this is to have your handler call the old handler as a subroutine, and then perform additional actions when the old handler returns. In other words, you can insert additional processing both before the old handler is called and after it is called.

The C translator library has a function for chaining interrupts called _chain_intr .

To describe a function that acts as an interrupt handler, use the interrupt keyword.

Such a function is terminated by a return instruction from the IRET interrupt. For it, commands to save registers at the input and restore them when exiting the interrupt handler are automatically generated. An example of using the interrupt keyword to define an interrupt handler function:

void interrupt far int_funct(...) ( // Interrupt handler body )

The interrupt handler function must be a far function, since the interrupt vector table contains full addresses in the format<сегмент:смещение>.

The interrupt keyword is also used to describe variables for storing interrupt vectors:

void (interrupt (far *oldvect)(...);

Use the _dos_setvec function to set your own interrupt handler. This function has two parameters - the interrupt number and a pointer to the new interrupt handler function.

For example:

_dos_setvect(0x16, my_key_intr);

In this example, interrupt number 16h (software interrupt for reading data from the keyboard) is set to a new interrupt handler my_key_intr.

If you need to find out the address of an old interrupt handler by its number, the best way is to use the _dos_getvect function, which takes the interrupt number as a parameter and returns a pointer to the corresponding handler.

For example:

old_vector = _dos_getvect(0x16);

To organize a chain of interrupts, use the _chain_intr function. This function takes the address of the old interrupt handler as a parameter.

BEEPER program

The BEEPER program (Listing 4.1) is a simple example that illustrates the use of all three of the interrupt functions listed above.

Listing 4.1. FILE beeper\beeper.cpp

#include #include #include void main(void); void interrupt far timer(...); void interrupt (far *oldvect)(...); // Variable for counting timer interrupts volatile long ticks; void main(void) ( // Reset the counter ticks = 0L; // Remember the address of the old // interrupt handler oldvect = _dos_getvect (0x1c); // Set the new interrupt handler _dos_setvect (0x1c, timer); printf("\nTimer set. Press any " " key...\n"); getch(); // Restore the old interrupt handler _dos_setvect (0x1c,oldvect); ) void interrupt far timer(...) ( // Increment the timer interrupt counter ticks++; / / If the counter value is a multiple of 20, // send a signal to the computer speaker if((ticks % 20) == 0) ( asm mov bx,0 asm mov ax, 0E07h asm int 10h ) // Call the old interrupt handler _chain_intr (oldvect) ; )

This program embeds its own timer interrupt handler that will be called approximately 18.2 times per second. The built-in interrupt handler counts timer interrupts and, if the value of the corresponding counter is a multiple of 20, the computer's speaker beeps.

At the end of the job, the new timer interrupt handler calls the old handler with the _chain_intr function.

After installing the new timer interrupt handler, the main program waits for the user to press any key. It then restores the old contents of the interrupt vector.

4.4. Features of processing hardware interrupts

Hardware interrupts are generated by computer devices, as a rule, when they complete data exchange operations or when they change state. Depending on the type of device, the interrupt handler can perform certain functions. For example, when a timer is interrupted, the corresponding handler increments the contents of the counter located in RAM. Programs can determine the current time from the contents of this counter.

Unlike software interrupts, which are scheduled to be triggered by a program or driver, hardware interrupts always occur asynchronously with respect to running programs. In addition, several interrupts can occur at the same time!

In order for the system not to get lost when deciding which interrupt to service first, there is a special priority scheme. Each interrupt is assigned its own priority. If multiple interrupts occur at the same time, the system prioritizes the highest priority, deferring other interrupts for a while.

The priority system is implemented on two Intel 8259 chips (or similar). Each chip is an interrupt controller and handles up to eight priorities. Chips can be combined (cascaded) to increase the number of priority levels in the system.

Priority levels are abbreviated as IRQ0 - IRQ15 .

The IBM PC/XT type computer had only one interrupt controller chip installed. The priorities depended linearly on the interrupt level number. IRQ0 was the highest priority interrupt, followed by IRQ1 , IRQ2 , IRQ3 , and so on.

The IRQ2 interrupt in the IBM PC/XT was reserved for future system expansion. In IBM PC / AT computers, the IRQ2 interrupt began to be used to cascade two 8259 interrupt controllers. The added priority levels of interrupts IRQ8 - IRQ15 in these computers are prioritized between interrupts IRQ1 and IRQ3.

Here is a list of hardware interrupts, arranged in descending order of priority:

Number Description
8 IRQ0 - interval timer interrupt, occurs 18.2 times per second
9 IRQ1 - keyboard interrupt
A IRQ2 - used to cascade hardware interrupts
70 IRQ8 - real time clock interrupt
71 IRQ9 - interrupt from the EGA controller
72 IRQ10 - reserved
73 IRQ11 - reserved
74 IRQ12 - reserved
75 IRQ13 - interrupt from the arithmetic coprocessor
76 IRQ14 - interrupt from the hard disk controller
77 IRQ15 - reserved
B IRQ3 - interrupt asynchronous port COM2
C IRQ4 - interrupt asynchronous port COM1
D IRQ5 - hard disk controller interrupt (IBM PC/XT only)
E IRQ6 - interrupt generated by floppy disk controller
F IRQ7 - printer interrupt

From this list, you can see that the interval timer interrupts have the highest priority, followed by the keyboard interrupt. Printer interrupt has the lowest priority.

To manage the priority schemes, you need to know the internals of the 8259 interrupt controller.

Incoming interrupts are stored in the interrupt request register IRR. Each of the eight bits in this register corresponds to a different interrupt.

Before issuing an interrupt request to the processor, the contents of the eight-bit interrupt mask register IMR are checked. If an interrupt of this level is not masked, then an interrupt request is issued.

The most interesting from the point of view of programming the interrupt controller are the IMR interrupt mask registers and the interrupt control register.

On IBM PC/XT computers, the interrupt mask register is 21h and the interrupt control register is 20h. On IBM PC/AT computers, the first 8259 controller has the same addresses as on the IBM PC/XT. The interrupt mask register of the second controller has the address A1h, the interrupt control register has the address A0h.

The bits in the interrupt mask register correspond to IRQ numbers. In order to mask a hardware interrupt of any level, it is necessary to write the mask byte into the mask register. In this byte, set to 1 those bits that correspond to maskable interrupts. For example, to mask interrupts from floppy drives, write the binary number 01000000 to port 21h.

Here is the line of the program that masks the interrupt from the floppy disk:

outp(0x21, 0x40);

To "animate" floppy interrupts, use the following line (which will unmask all interrupts):

outp(0x21, 0);

Note that in the example above, we masked the interrupt from the floppy drive, all other devices continued to work normally. If we issued a CLI machine instruction, then all hardware interrupts would be disabled. This would, for example, cause the keyboard to be locked.

Another note regarding hardware interrupt handling.

If you are completely replacing the standard hardware interrupt handler, do not forget to write byte 20h to port address 20h (A0h for the second 8259 controller) at the end of the program. These steps are required to clear the ISR. This allows the processing of interrupts with a lower priority than the one that was just processed.

If you are handling a 1Ch interrupt, then the above addition at the end of the interrupt handler is not necessary, since this interrupt is software-based and is called from the timer's hardware interrupt handler.

Before we conclude our study of interrupts, let's ask ourselves the question - is it possible to mask a non-maskable interrupt? It turns out you can!

Of course, if the interrupt signal came to the input of a non-maskable interrupt of the processor, nothing can be done - the interrupt will inevitably occur. But the computer has circuits that block the input of the NMI processor NMI.

For an IBM PC/XT computer, NMI masking is controlled by port address 0A0h. If you write 0 to it, the NMI will be disabled, if 80h it is enabled.

Similarly for the IBM PC/AT, bit 7 of port 70h controls NMI masking. Writing byte 0ADh to port 70h will disable the NMI, and writing byte 2Dh will enable the interrupt.

Note that we do not disable the NMI "inside" the processor - this is impossible by definition, we "do not allow" the interrupt signal to the NMI input.

Lecture №12

Interrupt system of 32-bit microprocessors i80 x86.

Operation of the interrupt system in real mode

Questions

1. The concept of interruption

2. Interrupt classification

3. interrupt system.

· Hardware

· Interrupt System Software

· Interrupt vector table

4. Interrupt Handling in Real Mode

Interruption means the temporary interruption of the main process of computing to perform some planned or unplanned actions caused by the operation of the hardware or program.

Those. it is a process that temporarily switches the microprocessor to the execution of another program and then returns to the interrupted program.

By pressing a key on the keyboard, we initiate an immediate call to a program that recognizes the key, enters its code into the keyboard buffer, from which it is read by another program. Those. for a while, the microprocessor interrupts the execution of the current program and switches to the interrupt routine, the so-called. about interrupt handler. After the interrupt handler completes its work, the interrupted program will continue execution from the point where it was interrupted.

The address of the interrupt handler program is calculated from the interrupt vector table.

The interrupt mechanism is supported at the hardware level.

Interrupt classification

Depending on the source, interrupts are divided into

· hardware- arise as a reaction of the microprocessor to a physical signal from some device (keyboard, system clock, keyboard, hard drive, etc.), these interrupts are asynchronous in time of occurrence, i.e. occur at random times;

· software- are called artificially using the appropriate command from the program ( int ), designed to perform some actions of the operating system, are synchronous;

· exceptions- are the reaction of the microprocessor to a non-standard situation that arose inside the microprocessor during the execution of some program instruction (divide by zero, interrupt by flag TF (trace)).

General classification of interrupts

· external- are caused by events external to the microprocessor

(essentially it is a group of hardware interrupts) There are no nested interrupts!

· internal- occur inside the microprocessor during the computational process (in essence, these are exceptional situations and software interrupts).

External interrupts occur at the signal of some external device.

External interrupts are divided into unmasked and masked.

Due to the fact that there are two special external signals among the input signals of the processor, with which you can interrupt the execution of the current program and thereby switch the operation of the central processor. These are signals NMI (no mask interrupt , non-maskable interrupt) and INTR (interrupt request , interrupt request).

Maskable interrupts generated by the interrupt controller at the request of certain peripherals. Interrupt controller (made in the form of a special microcircuit i8259A) supports eight levels (lines) of priority; one peripheral device is “attached” to each level. Maskable interrupts are often referred to as hardware interrupts..

On a PC, starting with the IBM PC AT, based on the i80286 microprocessor, two i8259A interrupt controllers are used; they are connected in series in a cascaded manner, which increases the number of external interrupt sources to 15 (8 each).

Let's pay attention . Chip i The 8259A is programmable.

Nonmaskable interrupts (they say that it is one, because it is fed to the output of the microprocessor NMI ) initiate sources that require immediate intervention from the microprocessor.

!

In the real and protected modes of the microprocessor, interrupt processing is carried out by fundamentally different methods.

interrupt system. Hardware and software of the interrupt system

The interrupt system is a combination of software and hardware that implements the interrupt mechanism.

To hardware interrupt systems include:

· microprocessor pins- signals are generated on them that notify the microprocessor either that some external device “ask to pay attention to it” ( INTR) , or that urgent processing of some event is required or a catastrophic error(NMI)

INTR - output for input interrupt request signal,

NMI - output for input NMI signal

INTA - output for weekend a confirmation signal for the receipt of an interrupt signal by the microprocessor (this signal is sent to the input of the 8259A controller microcircuit of the same name;

· programmable interrupt controller 8259A (designed to capture interrupt signals from eight different external devices;it is made in the form of a microcircuit; usually two microcircuits connected in series are used, so the number of possible sources of external interrupts is up to 15 plus one non-maskable interrupt; it is he who generates the number of the interrupt vector and issues its data bus);

· external devices (timer, keyboard, magnetic disks, etc.)

To software tools interrupt systems Real mode include:

· interrupt vector table .

Occupies the first kilobyte of RAM (addresses 00000 h-003FFh) .

It contains addresses (vectors - "vectors" because two values ​​for specifying the address) of interrupt handlers and consists of 256 (0..255) elements of 4 bytes each:

2 bytes - new value for the register IP

2 bytes - new value for the register CS.

Location of interrupt vector table in processors i80286 and older is determined by the value of the register IDTR.

The interrupt vector table is initialized at system startup, but in principle can be changed and moved.

Each vector has its own number and is called the interrupt number.

· two flagsin flag register flags/flags:

IF (Interrupt Flag) - interrupt flag. Designed to mask (disable) hardware interrupts. If a IF=1 , the microprocessor handles external interrupts, if = 0, then ignores;

TF(Trace Flag) - trace flag. If it=1, then the microprocessor switches to command mode. In this mode, the microprocessor generates an internal interrupt number 1;

· microprocessor machine instructions: int, into(overflow interrupt), iret, cli, sti

Interrupt Handling in Real Mode

produced in three stages:

1) termination of the current program;

It should happen in such a way that you can then return and continue working. To do this, you must save the contents of the registers, as they are resources shared between programs.

Registers are required to be saved cs, ip, flags (pair CS:IP contains the address of the command to start execution with after return, flags- the state of the flags after the execution of the last command of the interrupted program).

!!! These registers are stored automatically by the microprocessor. Preservation of other registers - must be provided by the programmer!!!

The most convenient place to store registers is the stack.

After saving the registers on the stack, the microprocessor resets the flag bit IF (i.e. = 0) (!!! At the same time, the register is written on the stack flags still installed IF !!!) This prevents the possibility of nested external interrupts and damage to the registers of the source program due to uncontrolled actions on the part of the program - the handler of the nested interrupt. After the necessary context saving actions are completed, the hardware interrupt handler can enable nested interrupts with the command sti.

2) transition to execution and execution of the interrupt service routine;

Here the interrupt source is defined and the appropriate interrupt handler is called.

In the real mode of the microprocessor, 256 sources are allowed - according to the number of elements of the interrupt vector table.

Element structure:

· 2 bytes - the offset value of the beginning of the interrupt handler program from the beginning of the code segment

· 2 bytes - the value of the base address of the segment in which the handler program is located.

How to determine the address at which the interrupt vector with the number is located N?

offset el-that table of interrupt vectors = N*4

Full table size?4*256=1024

So in the second stage, the microprocessor

1. Determines the offset in the interrupt vector table by interrupt source number

2. Puts the first two bytes into a register IP

3. Puts the second two bytes into a register CS

4. Transfer control to address CS:IP

(It can also be interrupted by a request from a higher priority source. All interrupt sources have priority.)

3) return control to the interrupted program.

It is necessary to bring the stack to the state in which it was immediately after control was transferred to this procedure. To do this, the programmer must specify the necessary actions to restore the registers and clear the stack. !! This section must be protected from possible distortion of the contents of the registers (as a result of a hardware interrupt) using the command cli .

The last commands in the interrupt handler - sti, iret

sti - enable hardware interrupts (sets the flag IF=1 , has no operands).

iret - pop three words sequentially from the stack and place them respectively in registers ip, cs, flags.

During the execution of the computer of the current program inside the machine and in the environment associated with it (for example, in a technological process controlled by a computer), events may occur that require an immediate response to them from the machine.

The reaction is that the machine interrupts the processing of the current program and proceeds to the execution of some other program specifically designed for this event. Upon completion of this program, the computer returns to the execution of the interrupted program.

The process in question is called program interruption. It is fundamentally important that the moments of occurrence of events that require program interruption are not known in advance and therefore cannot be taken into account when programming.

Each event that requires an interrupt is accompanied by a signal notifying the computer - interrupt requests. The program requested by the interrupt request is called the interrupt program, as opposed to the interrupted program that was being executed by the machine before the request occurred.

The ability to interrupt programs is an important architectural property of a computer that allows efficient use of processor performance in the presence of several processes running in parallel in time that require control and maintenance by the processor at arbitrary times. First of all, this refers to the organization of parallel operation of the processor and peripheral devices of the machine, as well as to the use of a computer for real-time control of technological processes.

In order for the computer to be able, without requiring much effort from the programmer, to implement program interruptions with high speed, the machine must be given appropriate hardware and software, the totality of which is called the program interrupt system.

The main functions of the interrupt system are:

    storing the state of the interrupted program and making a transition to the interrupted program

    restoring the state of the interrupted program and returning to it.

The interrupt vector is the "initial state of the interrupting program" vector. The interrupt vector contains all the necessary information to jump to the interrupt program, including its start address. Each interrupt request (number) has its own interrupt vector, capable of initiating the execution of the corresponding interrupt program. Interrupt vectors are located in specially allocated fixed memory cells - the interrupt vector table.

The main place in the procedure for switching to an interrupting program is occupied by the procedure for transferring from the corresponding register (registers) of the processor to memory (in particular, to the stack) to save the current state vector of the interrupted program (so that you can return to its execution) and loading into the register (registers) the processor of the interrupt vector of the interrupting program, to which control of the processor passes.

Interrupt classification

Interrupt requests can occur within the computer itself and in its external environment. The former include, for example, requests when such events occur in the computer as an error in the operation of its equipment, an overflow of the bit grid, an attempt to divide by 0, an exit from the memory area set for a given program, a request for an I / O operation by a peripheral device, completion of an operation I / O by a peripheral device or the occurrence of an exception during this operation, etc. Although some of these events are generated by the program itself, the moments of their occurrence, as a rule, cannot be foreseen. Requests in the external environment may arise from other computers, from emergency and some other process sensors, etc.

The Intel 80x86 microprocessor family supports 256 priority interrupt levels triggered by three types of events:

    internal hardware interrupts

    external hardware interrupts

    software interrupts

Internal hardware interrupts, sometimes called failures, are generated by certain events that occur during program execution, such as an attempt to divide by 0. Assigning certain interrupt numbers to such events is hardwired into the processor and cannot be changed.

External hardware interrupts initiated by peripheral equipment controllers or coprocessors (for example, 8087/80287). Interrupt sources are connected to either the processor's non-maskable interrupt (NMI) pin or the maskable interrupt pin (INTR). The NMI line is usually reserved for interrupts caused by catastrophic events such as memory parity errors or a power failure.

Software interrupts. Any program can initiate a synchronous software interrupt by executing the instruction int. MS-DOS uses interrupts from 20H to 3FH to interact with its modules and application programs (for example, the MS-DOS function manager is accessed by executing the command int 21h). BIOS programs stored in ROM and IBM PC applications use other interrupts, higher or lower. This distribution of interrupt numbers is conditional and is not fixed in hardware in any way.

Interrupt vector table

In order to associate the address of the interrupt handler with the interrupt number, the interrupt vector table is used, which occupies the first kilobyte of RAM. This table is in the address range from 0000:0000 to 0000:03FFh and consists of 256 entries - far addresses of interrupt handlers.

The entries in the interrupt vector table are called interrupt vectors. The first word of the table entry contains the offset component, and the second word contains the segment component of the interrupt handler address.

Interrupt vector 0 is at address 0000:0000, interrupt vector 1 is at 0000:0004, and so on. In general, the address of the interrupt vector is found by multiplying the interrupt number by 4.

Table initialization is performed partly by the BIOS basic input/output system after testing the hardware and before the operating system starts booting, partly when MS-DOS boots. The MS-DOS operating system can change some of the interrupt vectors set by the BIOS.

Interrupt vector table

Number

Description

division error. Called automatically after executing the DIV or IDIV commands if an overflow occurs as a result of division (for example, when dividing by 0). Typically, when this interrupt is handled, MS-DOS displays an error message and stops the program from running. In this case, for the i8086 processor, the return address points to the instruction following the division instruction, and for the i80286 processor and later models, to the first byte of the instruction that caused the interrupt

Interruption of the step mode. Issued after each machine instruction is executed if the step trace bit TF is set in the flags word. Used for debugging programs. This interrupt is not generated after transferring data to segment registers with MOV and POP instructions.

Hardware NMI. This interrupt can be used differently on different machines. It is usually generated when a parity error occurs in RAM and when an interrupt is requested from the coprocessor.

Trace interrupt. Generated when executing a single-byte machine instruction with code CCh and is commonly used by debuggers to set a breakpoint

Overflow. Generated by the INTO machine instruction if the OF overflow flag is set. If the flag is not set, the INTO command is executed as NOP. This interrupt is used to handle errors when performing arithmetic operations.

Print a copy of the screen. Fired when the user has pressed a key In MS-DOS programs, it is commonly used to print a screen image. For the i80286 processor and above, it is generated when the BOUND machine instruction is executed if the value being checked is outside the specified range

Undefined opcode or instruction length greater than 10 bytes

Special case of no arithmetic coprocessor

IRQ0 - interval timer interrupt, occurs 18.2 times per second

IRQ1 - keyboard interrupt. Emitted when the user presses and releases keys. Used to read data from the keyboard

IRQ2 - used to cascade hardware interrupts

IRQ3 - interruption of the asynchronous port COM2

IRQ4 - interrupt asynchronous port COM1

IRQ5 - hard disk controller interrupt (IBM PC/XT computers only)

IRQ6 - an interrupt is generated by the floppy disk controller after the completion of the I / O operation

IRQ7 - interrupt from parallel adapter. Generated when the printer connected to the adapter is ready to perform the next operation. Usually not used

Video adapter maintenance

Determining the configuration of devices in the system

Determining the size of RAM

Disk system maintenance

Working with an asynchronous serial adapter

Advanced Service

Keyboard maintenance

Printer Maintenance

Run BASIC in ROM if available

Watch service

Interrupt handler that occurs when the user presses a key combination

Software interrupt, called 18.2 times per second by the timer hardware interrupt handler

Video table address for 6845 video adapter controller

Pointer to floppy parameter table

Pointer to graphics table for ASCII characters 128-255

Used by MS-DOS or reserved for MS-DOS

Interrupts reserved for user programs

Not used

IRQ8 - real time clock interrupt

IRQ9 - interrupt from the EGA controller

IRQ10 - reserved

IRQ11 - reserved

IRQ12 - reserved

IRQ13 - interrupt from the arithmetic coprocessor

IRQ14 - interrupt from the hard disk controller

IRQ15 - reserved

Not used

Reserved for BASIC

Used by the BASIC interpreter

Not used

Interrupts designated as IRQ0 - IRQ15 are external hardware interrupts.

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